Integrated circuit devices such as transistors are formed over semiconductor wafers. The devices are interconnected through metal lines and vias to form functional circuits. The process for forming the metal lines and vias are referred to as back-end-of-line processes. To reduce the parasitic capacitance of the metal lines and vias, the metal lines and vias are formed in low-k dielectric layers, which are formed of low-k dielectric materials having k values lower than 3.8, lower than 3.0, or lower than 2.5.
In the formation of the metal lines and vias, the low-k dielectric layers need to be etched to form trenches and via openings, followed by filling a metallic material into the trenches and via openings. Since the low-k dielectric materials can easily absorb detrimental substances such as moisture, a baking process is typically performed before the filling of the metallic material. During the baking process, the detrimental substances are removed from the low-k dielectric material through evaporation.
Conventionally, fixed baking process was adopted. In the fixed baking process, baking process conditions such as the time, the power, and the temperature are pre-determined. The fixed baking process, however, may cause over-baking or under-baking. When over-baking occurs, extra thermal budget is unnecessarily introduced. Conversely, when under-baking occurs, there may be detrimental substances remaining in the low-k dielectric material. The situation is further worsened since the amount of the detrimental substances various. For example, for different etching processes, the amount of the detrimental substances may change from etching process to etching process. Even in the same etching process, the amount of the detrimental substances may also change from wafer to wafer. This makes it difficult for solving the over-baking and under-baking problems.